1. Field of the Invention
Generally, the present disclosure relates to the manufacture of semiconductor devices, and, more specifically, to various methods of making an e-fuse for use on integrated circuit products and the resulting integrated circuit product.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPU's, storage devices, ASIC's (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements in a given chip area according to a specified circuit layout. Field effect transistors (NMOS and PMOS transistors) represent one important type of circuit element that substantially determines performance of such integrated circuits. During the fabrication of complex integrated circuits using, for instance, MOS technology, millions of transistors, e.g., NMOS transistors and/or PMOS transistors, are formed on a substrate including a crystalline semiconductor layer. A field effect transistor, whether an NMOS or a PMOS device, is a planar device that typically includes a source region, a drain region, a channel region that is positioned between the source region and the drain region, and a gate structure positioned above the channel region. The gate structure is typically comprised of a very thin gate insulation layer and one or more conductive layers that act as a conductive gate electrode. In a field effect transistor, the conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by applying an appropriate voltage to the gate electrode.
For many early device technology generations, the gate structures of most transistor devices was made using silicon-based materials, such as a silicon dioxide and/or silicon oxynitride gate insulation layer, in combination with a polysilicon gate electrode. However, as the channel length of aggressively scaled transistor devices has become increasingly smaller, many newer generation transistor devices employ gate electrode structures comprised of a so-called high-k gate insulation layer (k value of 10 or greater) and a gate electrode structure comprised of one or more metal layers, i.e., high-k/metal gate structures (HK/MG). Transistor devices with such an HK/MG structure exhibit significantly enhanced operational characteristics as compared to the heretofore more commonly used silicon dioxide/polysilicon (SiO2/poly) configurations.
One well-known processing method that has been used in recent years for forming a transistor with a high-k/metal gate structure is the so-called “gate last” or “replacement gate” technique. In general, the replacement gate process involves forming a basic transistor structure that includes a sacrificial or “dummy” gate insulation layer, a sacrificial or “dummy” gate electrode, sidewall spacers and source/drain regions in the substrate. The sacrificial gate insulation layer is typically made of silicon dioxide and the sacrificial gate electrode is typically made of polysilicon. After certain high-temperature process operations are performed, e.g., after the source/drain anneal process is performed to activate the implanted dopant materials and to repair any damage to the lattice structure of the substrate, the sacrificial gate electrode and the sacrificial gate insulation layer are removed to thereby define a gate cavity between the spacers where the “replacement gate,” i.e., the high-k dielectric/metal gate structure, will be formed.
In modern integrated circuits, a very high number of individual circuit elements, such as field effect transistors in the form of CMOS, NMOS, PMOS elements, resistors, capacitors and the like, are formed on a single chip area. In addition to the large number of transistor elements, a plurality of passive circuit elements, such as capacitors, resistors and the like, are typically formed in integrated circuits that are used for a plurality of purposes, such as for decoupling.
Due to the reduced size of circuit elements, not only the performance of the individual transistor elements may be increased, but also their packing density may be improved, thereby providing the potential for incorporating increased functionality into a given chip area. For this reason, highly complex circuits have been developed which may include different types of circuits, such as analog circuits, digital circuits and the like, thereby providing entire systems on a single chip (SoC). Furthermore, in sophisticated micro-controller devices, an increasing amount of storage capacity may be provided on a chip with the CPU core, thereby also significantly enhancing the overall performance of modern computer devices.
For a variety of reasons, the various circuit portions may have significantly different performance capabilities, for instance with respect to useful lifetime, reliability and the like. For example, the operating speed of a digital circuit portion, such as a CPU core and the like, may depend on the configuration of the individual transistor elements and also on the characteristics and performance of the metallization system coupled to the CPU core. Consequently, the combination of the various circuit portions in a single semiconductor device may result in a significantly different behavior with respect to performance and reliability. Variations in the overall manufacturing process flow may also contribute to further variations in the performance capabilities between various circuit portions. For these reasons, in complex integrated circuits, frequently additional mechanisms are used so as to allow the circuit itself to adapt or change the performance of certain circuit portions to comply with the performance characteristics of other circuit portions. Such mechanisms are typically used after completing the manufacturing process and/or during use of the semiconductor device. For example, when certain critical circuit portions no longer comply with corresponding device performance criteria, adjustments may be made, such as re-adjusting an internal voltage supply, re-adjusting the overall circuit speed and the like, to correct such underperformance.
In computing, e-fuses are used as a means to allow for the dynamic, real-time reprogramming of computer chips. Speaking abstractly, computer logic is generally “etched” or “hard-coded” onto a silicon chip and cannot be changed after the chip has been manufactured. By utilizing an e-fuse, or a number of individual e-fuses, a chip manufacturer can change some aspects of the circuits on a chip. If a certain sub-system fails, or is taking too long to respond, or is consuming too much power, the chip can instantly change its behavior by blowing an e-fuse. Programming of an e-fuse is typically accomplished by forcing a large electrical current through the e-fuse. This high current is intended to break or rupture a portion of the e-fuse structure, which results in an “open” electrical path. In some applications, lasers are used to blow e-fuses. Fuses are frequently used in integrated circuits to program redundant elements or to replace identical defective elements. Further, e-fuses can be used to store die identification or other such information, or to adjust the speed of a circuit by adjusting the resistance of the current path. Device manufacturers are under constant pressure to produce integrated circuit products with increased performance and lower power consumption relative to previous device generations. This drive applies to the manufacture and use of e-fuses as well.
Prior art e-fuses come in various configurations. FIGS. 1A-1B depict illustrative examples of some forms of prior art e-fuses. FIG. 1A is a plan view of a very simple e-fuse 10 comprised of conductive lines or structures 12 having a reduced-size metal line 14 coupled to the conductive structures 12. The e-fuse 10 may sometimes be referred to as a “BEOL” type e-fuse, as it is typically made using the materials used in forming various metallization layers in so-called Back-End-Of-Line activities.
FIG. 1B is a cross-sectional view of another type of e-fuse 15 that extends between two illustrative metal layers, M2 and M3, formed on an integrated circuit product. In general, the e-fuse 15 is comprised of schematically depicted conductive lines 16, 18 that are formed in the metallization layers M2, M3, respectively. A reduced-size metal structure or via 20 is conductively coupled to the conductive lines 16, 18. The e-fuse 15 may sometimes be referred to as an “I” type e-fuse due to its cross-sectional configuration. In some very early device generations, e-fuses were comprised of structures that included polysilicon line-type features as part of the e-fuse. The polysilicon line-type features for the e-fuses were typically patterned at the same time as was the polysilicon gate electrodes for the various transistor devices. A metal silicide material was formed on top of the polysilicon lines used for the e-fuse.
All of the above-described e-fuses typically worked by passing a sufficient current though the e-fuse such that, due to resistance heating, some portion or component of the e-fuse ruptured, thereby creating an open electrical circuit. The polysilicon-based e-fuses were programmed by passing a current through the fuse to cause the metal silicide material to rupture due to electromigration. Some types of e-fuses, such as BEOL e-fuses, require a relatively high programming current, e.g., about 35 mA or higher. Such a high programming current is generally not desirable for e-fuses, as such a high programming current will require a relatively larger programming transistor, which means increased consumption of valuable space on the chip. Moreover, a higher programming current degrades the sensing margin for sensing circuits that are used to determine whether or not the e-fuse is programmed, i.e., blown.
FIGS. 2A-2D depict one illustrative prior art technique used to form metal silicide based resistors on a prior art integrated circuit product 30. FIG. 2A is a cross-sectional view that schematically depicts the product at a point in fabrication wherein an illustrative transistor 36 has been formed in and above an active region defined in the substrate 32 by an illustrative isolation region 34. The transistor 36 is generally comprised of a gate structure 38 comprised of a gate insulation layer 38A and a conductive gate electrode layer 38B, sidewall spacers 42, a gate cap layer 40 and source/drain regions 44. Various other aspects of the transistor 36 are not depicted, e.g., doped well regions, halo implant regions, etc. Also depicted in FIG. 2A is a contact level dielectric material 50 that has been formed above the substrate 32. The contact level dielectric material 50 is intended to be representative in nature as it may be comprised of one or more layers of insulating material, e.g., silicon dioxide, silicon nitride, etc. The contact level dielectric material 50 may be formed by performing one or more known deposition processes, e.g., chemical vapor deposition (CVD). The product 30 is depicted at the point in fabrication wherein it is time to form conductive contacts to at least the source/drain regions 44 of the transistor 36.
Next, as shown in FIG. 2B, a resistor body 52 is formed above the contact level dielectric material 50. In one embodiment, the resistor body 52 may be formed by depositing a layer of a metal silicide, e.g., tungsten silicide, and thereafter patterning the deposited metal silicide material using known photolithography and etching tools and techniques. The metal silicide material may be initially deposited by performing, for example, a physical vapor deposition (PVD) process. The resistor body 52 may be formed to any desired thickness and length.
FIG. 2C depicts the product 30 after a layer of insulating material 54 is deposited above the product 30. The layer of insulating material 54 is intended to be representative in nature as it may be comprised of one or more layers of insulating material, e.g., silicon dioxide, silicon nitride, etc. The layer of insulating material 54 may be formed by performing one or more known deposition processes, e.g., CVD, and it may be formed to any desired thickness.
FIG. 2D depicts the device 30 after various conductive contact structures have been formed to establish electrical contacts to the source/drain regions 44 of the transistor 36 and to the gate electrode 38B of the transistor 36. More specifically, conductive contact structures 56 and 58 are formed so as to be conductively coupled to the resistor body 52, conductive contact structures 60 are formed so as to be conductively coupled to the source/drain regions 44 and a conductive contact structure 62 is formed so as to be conductively coupled to the gate electrode 38B of the transistor 36. Although simplistically depicted in FIG. 2D, the various conductive contact structures 56, 58, 60 and 62 may be formed at the same time or at different times in the process flow depending upon the particular application. Moreover, the conductive contact structures 56, 58, 60 and 62 shown in FIG. 2D are depicted as being formed of a single uniform material. In practice, the conductive contact structures 56, 58, 60 and 62 may be comprised of two or more conductive materials, e.g., a metal silicide region and a tungsten region coupled to the metal silicide region. The manner in which the conductive contact structures 56, 58, 60 and 62 are formed are well known to those skilled in the art. In practice, the conductive contact structures 56, 58 provide a conductive flow path for current that passes through the resistor body 52 to establish the desired resistance in the circuit that includes the resistor. Importantly, all or a portion of the conductive contact structures 56, 58 are formed at the same time as at least a portion of one of the conductive contact structures 60 and 62 is formed.
The present disclosure is directed to various methods of making a metal silicide e-fuse for use on integrated circuit products and the resulting integrated circuit product.